The present invention is concerned with digital data transmission and especially with systems, methods and apparatus for detecting and correcting skew in data streams transmitted over a signal path, especially from a transmitter end to a receiver end of the path. The invention also encompasses transmitters, receivers, transmission methods and reception methods, all for detecting and correcting skew in data streams for transmission over a path. The invention further comprises signals and signal paths carrying such signals.
The present specification describes techniques and functions applicable to the implementation of a general purpose, skew compensating interface that, for convenience, has been given the acronym RAUDI (xe2x80x9cReference Aligned Universal Digital Interfacexe2x80x9d). RAUDI will find particular application in systems having bitstreams with data rates above 2.5G bits/second, but is applicable to any data rate where an application is otherwise compromised by any type of timing skew.
In telecommunications systems the most obvious (but not the only) application will be in the Physical Layer. The techniques used in the RAUDI enable significant functionality, specifically but not exclusively:
The interface is non-intrusive; it neither affects payload throughput nor the payload continuity even if payload flow is continuous (there is no flow control). It is thus transparent to higher level functions.
Operation is independent of the overlying payload format and application, i.e. it is format agnostic.
The features and hence complexity can be chosen and widely and flexibly distributed to suit both the application and the available implementation technologies.
Any implementation scales well with data rate, with skew magnitude, with bus width and with rate of change of skew.
The overhead associated with the skew compensation process is minimal.
These collective functions offer advantages over other, known skew compensating schemes as will become apparent.
Referring to FIG. 1, a schematic diagram of a digital data communication link is depicted. A transmit side or transmit interface, generically indicated at TX, inserts a plurality of bitstreams 0 to n into a transmission channel for reception at a receive side, or receive interface, generically indicated at RX. The individual bitstreams collectively define a data bus. There is significance in the relative position of the bits in the respective bitstreams forming the bus. This relative positioning needs to be preserved at the receive end RX if the received data is to be useful to the recipient. However, the data channel imposes variable delays on the bitstreams such that the data bits in the bit-streams are no longer in the same relative time/phase position as they were at the transmit end. This phenomenon is known in the art as skew. Measures have to be taken to restore the bitstreams into the same relative position that they had at the transmit end. This restoration is known in the art as skew compensation or skew correction.
All bits in a bus are notionally valid within a given window of time. The position in time of these bits with respect each other can be significant in data communications and so must be controlled if the significance is not to be lost. In a synchronous transmit/receive system, the values on each bit are sampled at fixed intervals to re-align them but if the data is sampled when the data is invalid, errors will occur.
The spread in the delay Introduced across all bits of an interface and its associated communications medium is called the overall skew of the bus. Different skews also exist between individual bits within the bus and these cannot exceed the overall skew. That part of the skew which is equal to a whole number of bit periods is defined as gross skew; the remaining skew, which is less than one bit period, is defined as the fractional skew. A simplified representation of skew is shown in FIG. 3. Throughout the present specification, the sum of the gross and fractional skew is collectively defined as skew.
Skew is not fixed and can change over time (quickly or slowly) depending on many factors, such as temperature. Since these external factors are often outside the scope of any control, they are a fundamental issue in high speed data communication.
Traditional low speed interfaces are able to transfer data words as a bus across a communications medium without introducing significant delay between individual bits. If all bits in a word can be transferred across an interface and associated communications medium such that all individual bits are correctly aligned to within 1 bit period, a conventional synchronous interface can transfer data of any format without any overall skew-induced errors. This is indicated generically in FIG. 4, where it can be seen that the system requires a common clock to control data transfer at both the transmit and the receive ends of a communication channel.
As an aid to understanding the terminology employed in the art and in the present specification it may be useful to define terms as follows:
A medium is defined as any intervening substance, including free-space, that can be used as a mechanism for conveying information. Each medium requires a driver and a receiver that is compatible with both the medium and the technology used to implement the interface.
The combination of transmit interface, medium and receive interface is defined as a channel.
A signal path can be any path or route taken by a signal in passing from one location to another. This may be a communication channel, incorporating for example an electric cable, optical fibre and so on. Alternatively, it may include a storage device which can be static, such as RAM or other software type storage, or dynamic, such as tape and disk storage media. It may also include a computer network.
Skew can be introduced by all components of the path. As data rates have increased (and will continue to increase) and, with longer interconnects, media and implementation technologies are being pushed to the limits and it is often impossible to control the channel skew to within 1 bit period without some additional scheme for skew compensation. Even short path lengths introduce skew if data rates are high.
It will not be uncommon for skews of any magnitude to be introduced across a data bus such that the significance of individual bits within a bus sampled at a single instant appears to be lost. There is thus a very real need for techniques which can in some way measure, track (and compensate for), large amounts of skew, thus re-aligning the individual bits of a data bus and fully restoring them.
Skew can be present in a system as fractional skew, gross skew or both, depending on the position in the system and the timing schemes in force. It is thus important to understand the significance of any skew at each point in a system. Two main types of system are important here; a synchronous system and a plesiochronous system. Correctly designed asynchronous systems are naturally robust to timing errors and are not considered here.
FIG. 5 depicts a synchronous system in which data is passed between perfect re-timing elements and sampled according to a common clock that is passed to both sides of the channel. As long as the skew between data and clock at points X is less than one bit period, the system performs as anticipated the relative position of bits is maintained and the fractional skew is removed by the re-timing element (the gross skew is zero). However, if the skew at X is 1 bit period, to within the uncertainty of the re-timing element, the re-timing element can choose to sample individual bits from one bit position or the next. There is thus an uncertainty as to the required value of the data bit and a 50% chance that the wrong data bit is sampled. Since the fractional skew is subject to variation and the clock can be subject to jitter, this can cause the sampled data Y to wander between clock cycles in an uncontrolled fashion.
If all bits of the bus are around the same sampling point, it can be seen that the probability of sampling all bits correctly rapidly diminishes to zero. The performance of the system is then dominated by the skew performance of the channel and not by the rest of the system and becomes undeterministic.
Purists will recognise that this argument is incomplete, but the following rules can be deduced and hold true even if all arguments are known.
Rule 1
Where a synchronous system encompasses a channel whose overall skew is always less than 1-bit period, correct operation is attained and fractional skew is removed by the receiving timing element.
Rule 2
Where a channel having overall skew of more than 1-bit period is terminated by a synchronous interface, the system behaviour is undeterministic, even if the correct gross skew is removed from the sampled data in the receiver.
On the basis of rules 1 and 2 it can be assumed that if gross skew is present in the channel, both skew measurement and compensation are impossible in a synchronous system. FIG. 6 depicts the overall system under consideration. However, it can be deduced that if it were possible to insert skew compensation on the transmit side of the channel (as shown FIG. 6) and if it were possible to provide the skew correcting parameters at this point, then the sampling point of the timing element is not compromised and perfect data is received.
Note also that even if the skew compensation block introduces latency that contributes to the gross skew, this can also be captured in the skew compensation parameters and so removed. Furthermore, by the application of rule 1, it can be seen that the skew compensation block need only remove the gross skew from the channel, the fractional skew being removed by the receive re-timing block.
Turning now to FIG. 7, the details of how the skew compensation parameters are passed are overlayed on FIG. 6. By applying rule 1, it can be seen that the skew between re-timing stages in this path must always be less than 1 bit period. This constrains the channel skew to be less than 1 bit and so gross skew compensation is precluded. Rule 3 can be deduced as follows:
Rule 3
The maximum skew that can be removed by a synchronous skew compensating interface is the fractional skew ( less than 1 bit). In other words, a re-timing stage is the best possible synchronous skew compensation available.
Because of the fundamental incompatibility of synchronous systems in the presence of gross skew, the use of plesiochronous systems has become widespread in high speed interfaces. Plesiochronous systems rely on the repetitive nature of a data bit to deduce the clock period associated with the data. A continuous clock of this frequency can thus be extracted and aligned with the data to allow a subsequent system (asynchronous or synchronous) to sample it correctly. At certain points in the plesiochronous system, this transition from data to clock with data is made and vice versa.
It is an artefact of a plesiochronous system that individual data bits are allowed to have completely ambiguous phase and hence skew relationships with other data bits and the only timing significance associated with the data is with its own extracted clock. There is thus no timing significance between any data bits. They can thus be regarded as permanently skewed. Since they are permanently skewed, gross skew introduced in a channel is a naturally tolerated parameter no matter how large it is.
It is thus possible to define the following rule:
Rule 4: Where a channel is terminated by a plesiochronous interface, individual data bits can be subjected to an infinite amount of skew without loss of data.
In the system depicted in FIG. 8, the source of data generates m bits which are multiplexed to n-bits at a higher rate by a serialiser and media driver for transmission over the channel. The channel introduces skew and the payload is removed in the media receiver and is demultiplexed back to the original m bits and an additional m clocks in a deserialiser.
It is however important to note that although the channel is carrying the payload correctly, the significance of the data to the applications has been lost in the presence of gross skew.
It is also an artefact of plesiochronous systems that when the data is extracted it is realigned to its own clock and so fractional skew is removed. The plesiochronous receiver also has to maintain the alignment of data and clock in the presence of jitter and changes in skew. Since this a natural artefact of the plesiochronous receiver, it is possible to define rule 5 as follows:
Rule 5: When a channel is terminated in a plesiochronous receiver, it removes the fractional skew.
By combining Rules 4 and 5 it can be seen that gross skew is the only type of additional skew compensation required when a channel is terminated at a plesiochronous interface. It is noteworthy that designs for such plesiochronous translators can themselves introduce large amounts of gross skew into the data (not just absolute delay) thereby exaggerating the timing uncertainty of any medium-introduced skew. It is for this reason, that most skew compensating schemes place the skew compensation immediately after the plesiochronous receiver.
The context in a typical system is depicted in FIG. 9. This shows the context for any skew compensating scheme and has a single location for the skew compensation blocks applicable to RAUDI or other schemes.
The context is shown in FIG. 9 but is not limited to any specific data transmission method. The general nature of this part of the discussion highlights the broadbased application of the invention but also allows the introduction of some of the common and scheme specific requirements for a skew compensation scheme to be introduced as the description becomes more specific.
Data is sent from the source 1 at the top of FIG. 9 and is ultimately delivered to the destination 2 at the bottom. In this illustration, the path 3 carries the plesiochronous data and introduces large amounts of gross skew. Since the channel is terminated in a plesiochronous interface 4 (rules 4 and 5) the challenge for the designer of a skew compensation scheme is to find the best method to measure, track and compensate for the gross skew while working to link integrity and implementation constraints.
In general terms, the channel skew characteristics are measured 5 and then used to create the parameters required for the skew compensation block 6. The skew compensation block thus applies the inverse skew function to the measured channel skew function. Detection of errors can be important but no specific error detection block is shown in this particular depiction. This is because not all schemes can naturally detect errors whereas RAUDI can do so within the skew compensation block. For the correct operation of a plesiochronous interface there must be sufficient numbers of transitions in the received data to allow a clock to be recovered and to align it correctly with the recovered data eye. This is widely understood by the skilled man and, where the data transition density is too low, this requirement can be met through the use of paired scramblers/descramblers in the transmit and in the receive data paths.
In the RAUDI case, the interface is data format agnostic and so does not have prior knowledge of the transition density associated with the data it is transmitting. It can thus be most important that the data is scrambled for the correct operation of the plesiochronous devices, as will be explained more fully later.
Since the plesiochronous interface is contained within the scope of the skew compensation scheme this skew can also be removed. The transition density scrambler (or another scrambler) can also be used to ensure that individual bit streams are not highly correlated (i.e. similar) to each other (e.g. where all data bits are at logic xe2x80x980xe2x80x99 for extended periods). This assists with RAUDI performance (see later) by reducing false correlations in its skew measurement scheme.
There, the key function of the plesiochronous receiver is that it tracks small changes in skew and constantly removes it. In the steady state, the gross skew rarely changes. The main impairment to this fine tracking is the rate at which changes in skew can be tracked. This is an artefact of the implementation of the plesiochronous receiver. Theoretically, a perfect receiver can always track rates of change in skew which are less than 1-bit per bit period i.e. if the data moves by less than one bit within its own period. If the rate of change in skew is within this limit, the recovered data and associated clock are dynamically realigned to track the change autonomously. The data at the output of the plesiochronous interface is thus xe2x80x98bit lockedxe2x80x99 with respect to its own clock and will track and hence remove the fractional contributor to the skew. The gross skew (possibly even 100""s of bits) across the whole bus is still present at the output of the medium receiver.
At the output of the plesiochronous receiver there are the recovered clock and data busses, each data stream being synchronously aligned with its own clock but with arbitrary phase between these and the other bits/clocks. It is at this point where implementers of skew compensation schemes (including RAUDI) find it convenient to operate synchronously within a single clock domain. The data is re-timed onto a single clock using a circular buffer, which an expert in implementation can make error free. The circular buffer is in essence a buffer-with separate write and read ports whose addresses are kept apart so that the re-timed data is always stable when it is read.
At the output of the circular buffer, the data has had fractional skew removed and has been re-timed onto a single clock. Up to this point most aspects of skew compensation schemes are common. In general terms these schemes all require transmit functionality, receive functionality and a medium to transfer data containing payload and signalling. Some schemes combine signalling and the payload and others keep them separate. Note that some of these schemes are intrusive and affect the payload directly in some way; others do not affect payload at all. It should thus not be assumed that the path labelled payload in the figure has continuity; some schemes periodically disrupt this path. RAUDI is totally non-invasive as it neither modifies nor interrupts the payload at any time.
Various competitive techniques for the removal of the gross skew and their relative merits and limitations will now be described in order to place the present invention and its likely impact on digital transmission in proper perspective. The RAUDI design has major advantages over other prior art schemes, including those recently specified as Industry Standards by the IEEE.
FIG. 9 remains relevant to the subsequent discussion.
1) Sending a Training Sequence.
When a link is initialising, an expert implementer can devise a sequence of training data that is transmitted on all data bits prior to the payload. The receiving device can use knowledge of that sequence to derive the skew between individual bits and thus compensate for them.
This scheme has the following advantages:
The use of training sequences is well established in certain other applications where the medium characteristics are unknown. The use of training sequences for skew compensation is however less well established.
This approach is data agnostic.
This scheme has the following disadvantages:
While the training sequence is being sent, payload cannot also be sent. The training sequence blocks useful payload upon initialisation and on any subsequent re-training or verification of the medium characteristics. This scheme thus compromises payload continuity and throughput in systems where flow control is not available at the next layer in the hierarchy, payload will be corrupted for the duration of the training sequence, introducing errors into the payload that must be detected at higher levels of control. The interface is thus not self-contained and cannot be used in high integrity systems.
Genuine payload must not be mistaken for the training sequence to any high probability. If the content of the payload is unknown, there is always a finite probability that the payload and the training sequence will be confused, leading to communication errors.
If signalling is not to interrupt the payload, provision for a separate signalling path is also required. Skew compensation does not occur continuously; it only occurs at specific times.
In the presence of gross errors, there is no method for detecting these until the next training sequence is sent. The interface will propagate errors until then. If the frequency of training is high, this degrades payload throughput but increases the chance of early detection of errors. If the frequency of re-training is infrequent it is more likely that errors will be detected by devices that are higher in the hierarchy before the link itself detects the error. There is thus no fast detection of link failure that does not rely on other (higher) levels of control. It is also necessary to choose a re-training rate that depends on how likely errors are to occur and this may be impossible to predict as it depends on external factors. There are thus aspects of performance that depend on the environment rather than the implementation. RAUDI is distinct from the scheme as it uses the data itself to characterise the channel.
2) Adding an Overhead to the Transmission Rate.
In this scheme, incoming payload at p bits/s is transmitted over a link at a higher rate of h bits/s. This allows (h-p) bits/s of signalling to be transmitted over the link in parallel with the payload. This overhead is also used to transmit frame alignment codes which an expert implementer can use to compensate for the detected skew. An example of such an interface is the IEEE XAUI interface as used between XGXS blocks as specified in IEEE802.3ae.
This scheme has the following advantage:
Characterisation of the medium-and signalling is performed over the same number of ports as the original medium drivers/receivers and so has a zero port connection overhead.
This scheme has the following disadvantages:
All bits of medium drivers and receivers have to operate at a higher rate, making them more demanding on design (noise immunity, emc and power consumption). The extra capacity that these have is not then used to carry any additional payload.
Because a rate change is required additional references or clock generators are required to provide the new rate, adding to design complexity and implementation issues.
In the XAUI example the basic payload rate is 2.5 Gb/s and the final medium transmission rate is 3.125 Gb/s; a significant overhead.
3) Using Knowledge of the Payload to Derive Framing Information
Under this scheme the skew compensation can only work if the data contained in the payload has a known frame structure. An example of such an interface is the SUPI interface as specified in IEEE 802.3ae. In this example, the payload already contains SONET framing information that an expert implementer can use to characterise and compensate for skew.
This scheme has the following advantage:
Characterisation of the medium is performed over the same number of bits as the original medium drivers/receivers and so has a zero port connection overhead.
This scheme has the following disadvantages:
This technique cannot be used where there is no overlying frame structure in the payload (i.e. it does not work if the format of the data is totally arbitrary). The scheme does not thus lend itself to generic interfaces. This technique does not work if there is an underlying frame structure, but this is not known in advance. The interface only interacts with other devices that carry payload in the same format as that catered for, thereby making it application specific.
Because the transported payload is carried in a frame, the framing overhead erodes the payload carrying capacity of the link to below its maximum capacity.
Where the overlying frame does not already accommodate link layer signalling, this feature cannot be implemented without an additional parallel signalling path (an interface port overhead).
The maximum skew compensation that can be performed is limited by the length of the overlying frame (the longer the frame, the more skew can be compensated for). In the case of OC192 SONET for SUPI framing, the period of the frame is fixed and long. Although this provides for good skew compensation properties, the time for gross errors to be detected can be extended. Without the scope to reduce the length of the frame, this restricts the ability of the interface to quickly detect and signal link errors. The performance is thus limited by the format of the data itself rather than the chosen implementation.
4) Using a Parity Bit to Estimate the Skew.
Although no serious proposals for this type of scheme have been put up, the technique is nevertheless feasible and its features are therefore worthy of comparison against the other techniques as it has the same bit overhead as RAUDI but is impractical to use in any serious application. It is also important not to confuse this scheme with the RAUDI scheme. It is for this reason that in the present description, the extra over-head bit in the RAUDI scheme is described as the reference bit. The difference between this technique and the parity bit technique will become clear as this explanation continues.
Under the parity bit scheme, parity is calculated across the data bits, i.e. in a row cutting across the bitstreams in the bus, and the result sent across the interface on a separate parity port. In the receiver, all the potential skew combinations are constructed and an associated parity calculated. The parity for each possible skew combination is compared with the received parity over a period of many bits while trying to establish a reliable and exact match to the parity sequence.
Advantages of this scheme are:
It can compensate for skew across data with arbitrary format (in other words, it is data agnostic).
Disadvantages of this scheme:
If more then a few bits of skew compensation are required, either the hardware becomes complex, owing to the numerous skew possibilities introduced by the medium, or the time to find the correct skew compensation becomes extended (the implementer decides which). In either case the performance and complexity are inferior to the RAUDI scheme.
As the bus width increases or the skew increases, the complexity of implementation scales badly according to a power law.
If a single parity bit is used there are multiple possible matches of parity for an odd number of bits that have not yet been skew compensated. The time to characterise, and compensate for, the skew is thus dependent on the data itself and so is not deterministic.
To make the scheme practical, it may be necessary to calculate several bits of parity and add these as an overhead on the interface.
The invention therefore provides, in one aspect, a digital data communication system incorporating means to detect skew between n parallel digital data bitstreams relative to one another, the system comprising;
a multiplexer arranged to sample bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream;
a driver arranged to insert said n parallel bitstreams and said reference bitstream into a signal path;
a receiver arranged to retrieve the n parallel bitstreams and the reference bitstream from the signal path;
a reference bitstream extractor arranged to recover the reference bitstream; and
a comparator arranged to compare said extracted reference bitstream with said n retrieved parallel data bitstreams to produce outputs indicative of the offset of each of said parallel bitstreams relative to said reference bitstream.
The path may comprise a transmission channel. It may alternatively comprise a storage device. The storage device may comprise a dynamic recording and playback device, such as a tape or disk recorder or a static storage device, such as a random access memory. The path may comprise a computer network.
The system may further comprise a corrector to correct skew between said n parallel data bitstreams in accordance with said offset indicative outputs. The comparator may comprise a correlator arranged to correlate the data bitstreams with the reference bitstream over a plurality of spaced time intervals.
There may be a scrambler to scramble the bitstreams prior to insertion in the said path and a descrambler arranged to descramble the bitstreams recovered from the path.
The correlator may comprise:
an input FIFO buffer connected to receive the n parallel data bitstreams and the reference bitstream from the path;
at least one correlator connected to receive time-spaced samples of the data bitstreams passing through the input buffer and to compare them with the reference bitstream passing through the input buffer, whereby to produce offset outputs representative of the closeness of the match between the reference and the data bitstreams.
The system may further comprise a controllable delay device arranged to adjust the relative timing between data bitstreams in accordance with said offset outputs, whereby to correct the received data bitstreams for skew.
In addition, the system may further comprise:
a sampler having:
an input connected to an offset output of the correlator, said offset output representing the required amount of skew correction;
an output connected to a control input of the said controllable delay device; and
a control input controlling the passage of offset values between said offset output and said control input of said controllable delay means;
the correlator having an output arranged to extract a signal corresponding to the sample sequence used by the said multiplexer to form the reference bitstream; and
said correlator output connecting the said signal to the control input of the sampler;
whereby the said signal controls the sampler to permit passage of a new offset value to the said controllable delay means only when there is a single occurrence of a correlation offset across the bitstreams at any given instant.
The system may also comprise a further multiplexer connected to the said path so as to insert message signals into the path. The further multiplexer can transmit said message signals by modulation of the reference bitstream. Alternatively, said further multiplexer is a time division multiplexer connected downstream of the multiplexer used to form the said reference bitstream, whereby to multiplex the message signals with the reference bitstream. Alternatively, said further multiplexer is connected to a direct output of said multiplexer used to form the said reference bitstream and to an inverted output from said multiplexer, and a source of message signals is connected to said further multiplexer such that message signals are sent by selective transmission of the direct or the inverted versions of the output from said multiplexer.
In addition, the said further multiplexer may comprise:
a first time division multiplexer connected to an inverted version of said data bitstreams;
a second time division multiplexer connected to a direct version of said data bitstreams;
and wherein outputs from said first and second time division multiplexers are connected to the input of said multiplexer used to form the said reference bitstream, whereby to multiplex the message signal with the inverted version of the data bitstreams.
The system may further comprise a predictor connected to said comparator and arranged, in response to a signal derived from said comparator, corresponding to a sampling sequence used to form the said reference bitstream, to predict that bitstream which next correlates best with said reference bitstream.
There may be means to signal a fault condition when the predicted bitstream does not correlate as expected.
Where the said path comprises an optical fibre and a laser arranged to insert data bitstreams into said path, a control device may be arranged to shut down said laser in response to the generation of a fault condition.
In a second aspect, the invention comprises a method of detecting skew between n digital data bitstreams relative to one another, the method comprising;
arranging said digital data into n parallel bitstreams;
sampling bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream;
inserting said n bitstreams and said reference bitstream into a signal path;
retrieving said n bitstreams and said reference bitstream from said signal path; and
comparing the retrieved reference bitstream with said n retrieved parallel data bitstreams in order to produce outputs indicative of the offset of each of said n parallel bitstreams relative to said reference bitstream.
In this method said comparing step may comprise correlating said reference bitstream and said data bitstreams over a plurality of spaced time intervals.
The method may further comprise correcting the skew of said n parallel data bitstreams in accordance with said offset indicative outputs.
The method may further comprise scrambling the bitstreams prior to insertion into said path and descrambling the bitstreams after recovery from said path.
The correlating step may comprise:
passing the recovered n parallel data bitstreams and the reference bitstream through an input FIFO buffer; and
correlating recovered time-spaced samples of the data bitstreams passing through the input buffer with the reference bitstream passing through the input buffer, whereby to produce outputs indicative of the offset of the reference bitstream and the data bitstreams.
The method may further comprise the step of adjusting the relative timing between data bitstreams in accordance with said offset outputs of the correlator by means of a controllable delay device, whereby to correct skew between the data bitstreams.
This method may further comprise:
passing said offset outputs of the correlator to a control input of the said controllable delay device through a controllable sampler;
extracting from the correlator a signal corresponding to the sample sequence used to form the reference bitstream; and
only permitting passage of a new offset value to the said controllable delay means when there is a single occurrence of a correlation offset across the bitstreams at any given instant.
The method may further comprise sending signalling messages over the said path. This signalling is preferably effected by connecting a message signal to an input of a time division multiplexer connected to the said multiplexer used to form the said reference bitstream, whereby to multiplex the message signal with the reference bitstream.
Alternatively, said signalling is effected by connecting a message signal to an input of a time division multiplexer connected to a direct output from the output of said multiplexer used to form the said reference bitstream and to an inverted output from said multiplexer, whereby to multiplex the message signal by selective transmission of the direct or the inverted versions of the output from the multiplexer.
The said signalling may be effected by:
a first time division multiplexer connected to an inverted version of said data bitstreams;
a second time division multiplexer connected to a direct version of said data bitstreams;
connecting the outputs from the first and second time division multiplexers to the input of said multiplexer used to form the said reference bitstream; and
connecting a message signal to an input of said first time division multiplexer, whereby to multiplex the message signal with the inverted version of the data bitstreams.
The method may comprise connecting a predictor to said comparator so as, in response to a signal derived from said comparator, corresponding to said sampling sequence used to form the said reference bitstream, to predict the data bitstream which next correlates best with said reference bitstream.
Further, the method may comprise signalling a fault condition when the predicted bitstream does not correlate as expected.
Where the path comprises an optical fibre and a laser arranged to insert data bitstreams into said path, there may be an additional step comprising shutting down said laser in response to the generation of a fault condition in the said path.
In a third aspect, the invention provides a digital data transmitter adapted to detect skew between n parallel digital data streams relative to one another, the transmitter comprising:
a multiplexer arranged to sample bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream; and
a driver arranged to insert said n parallel bitstreams and said reference bitstream into a signal path.
The transmitter may further comprise a controllable delay device responsive to signals retrieved from the said path indicative of the offsets of each of said data bitstreams relative to said reference bitstream, whereby to adjust the relative timing between data bitstreams so as to correct skew.
The transmitter may alternatively comprise a correlator arranged to correlate the data bitstreams with the reference bitstream recovered from the signal path so as to produce offset outputs indicative of the offset of each of said data bitstreams relative to said reference bitstream.
The digital data transmitter may further comprise a controllable delay device responsive to said offset indicative outputs whereby to adjust the relative timing between data bitstreams so as to correct the detected skew.
In a fourth aspect, the invention comprises a digital data receiver for n parallel data bitstreams received over a signal path, said receiver incorporating means arranged to detect skew between said n digital data streams relative to one another, comprising:
a receiver arranged to retrieve from said path said n parallel data bitstreams and a reference bitstream, said reference bitstream comprising sampled bursts of data from said n parallel bitstreams according to a sampling sequence;
an extractor arranged to recover said-reference bitstream; and
a comparator arranged to compare said extracted reference bitstream with said n received parallel data bitstreams in order to produce outputs indicative of the offset of each of said parallel bitstreams relative to said reference bitstreams
The receiver may further comprise a driver arranged to insert into said path, for reverse transmission to a transmit side of the said path, a signal representing the offset indicative outputs of the said comparator.
The receiver may alternatively comprise a corrector arranged to correct skew between said n parallel data bitstreams in accordance with said offset indicative outputs.
In the receiver, the comparator may comprise a correlator to correlate the data bitstreams with the reference bitstream over a plurality of spaced time intervals.
In a fifth aspect, the invention comprises a method of transmitting digital data over a signal path in such a way as to enable detection of skew between digital data bitstreams relative to one another, the method comprising;
arranging said digital data into n parallel digital data bitstreams;
sampling bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream; and
inserting said n bitstreams and said reference bitstream into said signal path.
In a sixth aspect, the invention comprises a method of receiving digital data from a signal path in such a way as to enable detection of skew between n parallel digital data bitstreams relative to one another, the transmitted data comprising said n parallel digital data bitstreams and a reference bitstream comprising sampled bursts of data from said n parallel bitstreams according to a sampling sequence, the method comprising:
retrieving said n parallel data bitstreams and said reference bitstream from said signal path;
extracting said reference bitstream; and
comparing said extracted reference bitstream with said n received parallel data bitstreams in order to produce outputs indicative of the offset of each said data bitstream relative to said reference bitstream.
This method may further comprise correcting skew between said n parallel data bitstreams in accordance with said offset indicative outputs.
In a seventh aspect, the invention comprises a digital signal comprising a plurality of n digital data bitstreams and a reference bitstream, said reference bitstream comprising a series of bursts of samples from said n data bitstreams, whereby skew between the data bitstreams may be detected.
In an eighth aspect, the invention comprises a digital signal comprising a plurality of n digital data bitstreams that have been corrected for skew by a method comprising the steps of:
arranging a source of digital data into n parallel bitstreams;
sampling bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream;
inserting said n bitstreams and said reference bitstream into a signal path;
retrieving said n data bitstreams and said reference bitstream from said signal path;
extracting said reference bitstream; and
comparing said extracted reference bitstream with said n received parallel data bitstreams in order to produce outputs indicative of the offset of each said bitstream relative to said reference bitstream.
In a ninth aspect, the invention comprises a digital signal comprising a plurality of n parallel data bitstreams that have been corrected for skew by a digital data transmission system, the system comprising;
a multiplexer arranged to sample bursts of data from said n parallel data bitstreams to form a reference bitstream;
a driver arranged to insert said n parallel data bitstreams and said reference bitstream into a signal path;
a receiver arranged to retrieve said reference bitstream and said data bitstreams from said signal path;
a comparator arranged to compare the recovered reference bitstream with the received parallel data bitstreams in order to produce outputs indicative of the offset of each of said parallel data bitstreams relative to said reference bitstream; and
an adjustable delay device arranged to adjust the relative timing between said data bitstreams in accordance with said offset indicative outputs.
In a tenth aspect, the invention comprises a digital signal comprising a plurality of n parallel data bitstreams that have been corrected for skew resulting from passage over a signal path of n parallel data bitstreams and a reference bitstream, said reference bitstream comprising sampled bursts of data from said n parallel data bitstreams according to a sampling sequence, skew having been corrected by a method of receiving transmitted data comprising:
retrieving said n parallel data bitstreams and said reference bitstream from said signal path;
extracting said reference bitstream;
comparing said extracted reference bitstream with said n retrieved parallel data bitstreams in order to produce outputs indicative of the offset of each said data bitstream relative to said reference bitstream; and
correcting the skew between said n parallel data bitstreams in accordance with said offset indicative outputs.
In an eleventh aspect, the invention comprises a digital data signal comprising n parallel data bitstreams and a reference bitstream comprising sampled bursts of said n parallel data bitstreams according to a sampling sequence.
In a twelfth aspect, the invention comprises a signal path carrying a digital data signal according to the preceding paragraph.
In a thirteenth aspect, the invention comprises a digital data communication system incorporating means to detect skew between n parallel digital data bitstreams relative to one another, the system comprising a transmit side and a receive side,
the said receive side comprising:
a multiplexer arranged to sample bursts of data from said n parallel bitstreams according to a sampling sequence to form a reference bitstream;
a driver arranged to insert said reference bitstream into a signal path for reverse transmission to the transmit side;
the said transmit side comprising:
a reference bitstream extractor arranged to recover the reference bitstream from the signal path; and
a comparator arranged to compare said extracted reference bitstream with said n parallel data bitstreams to produce outputs indicative of the offset of each of said n parallel bitstreams relative to said reference bitstream.
This system may further comprise a corrector to correct skew between said n parallel data bitstreams in accordance with said offset indicative outputs.
The receive side may further comprises a phase detector to detect the phase difference between the data bitstreams and a reference clock.
The receive side may yet further comprise a modulator to modulate said reference bitstream to indicate to the transmit side any detected phase error.
The modulator may comprise a multiplexer arranged to transmit selectively a direct or an inverted version of the reference bitstream.
The transmit side of the communication system may further comprise a transmitter arranged to insert said n parallel data bitstreams into said signal path, said transmitter further being controlled so as to minimise fractional skew.
The said transmitter on said transmit side is preferably controlled in accordance with error signals derived from a comparison of the relative phase between a reference clock and error signals output from a comparator arranged to detect skew between the n parallel data bitstreams and the said reference bitstream.
The said phase detector at said receive side is preferably arranged to indicate three phase states in which the reference clock is (i) in advance of or (ii) lags the data bitstream or (iii) the phase angle is unknown.
The said phase detector at the receive side may be arranged to suppress passage of output signals indicating either the first or the second phase states when the third phase state exists.
The said phase detector at the receive side is advantageously arranged to send an alternating signal when the third phase state exists.
The said multiplexer arranged to sample bursts of data may further comprise a comparator arranged to determine whether correlation exists between the sample burst of data currently being transmitted and the sample burst of data to be transmitted next.
The last mentioned comparator is preferably arranged to substitute a different sampling sequence when it is determined that said correlation exists, whereby to avoid false skew detection.
In a fourteenth aspect, the invention comprises a digital data communication transmitter, comprising:
a driver arranged to insert into a signal path n parallel digital data bitstreams;
a reference bitstream extractor arranged to extract a reference bitstream from said signal path, said reference bitstream comprising sample bursts of data from said n parallel data bitstreams;
a comparator arranged to compare said extracted reference bitstream with said n parallel data bitstreams to produce outputs indicative of the offset of each of said n parallel data bitstreams relative to said reference bitstream.
In a fifteenth aspect, the invention comprises a digital data communication receiver arranged to receive n parallel digital data bitstreams over a signal path, said receiver further comprising:
a multiplexer arranged to sample bursts of data from said n parallel digital data bitstreams according to a sampling sequence to form a reference bitstream; and
a driver arranged to insert said reference bitstream into said signal path for reverse transmission to a transmit side of the signal path.